2 to 1 multiplexer verilog code using conditional operator Verilog tutorial

This verilog tutorial shows how a 2 to 1 multiplexer can be designed in verilog using conditional operator"?". This way of implementing a circuit in verilog is called behavioral modelling. A multiplexer can also be modelled using strucural modelling which was illustrated in earlier blog post 2 to 1 multiplexer Verilog Code


Verilog code for 2 to 1 multiplexer using Conditional Operator

module mux2x1(a, b, sel, z);
    input a, b, sel;
    output z;
   
    assign z = sel? a:b;
   
endmodule

The input to the multiplexer is a and b. sel is the selector signal and z is the output. assign statement is used to assign input a or b to output z according to value of sel signal.

If sel is logic 0 then z = b and if sel is logic 1 then z = a.

Compilation and Simulation Result:

The code was compiled and simulated using verilog Software and the simulation trace is shown below:

Related Simulation:

See also VHDL code for the 2 to 1 multiplexer:

VHDL code for 2 to 1 multiplexer using when, select, if, case statements and structural model

Read also 2 to 1 multiplexer simulation in Proteus Professional:

4x1 and 2x1 multiplexer circuit simulation

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