Positive and Negative Edge Triggered D flip flop with VHDL example

A synchoronous system is one which contains elements which can be triggered to change internal state by applying clock pulse to the internal register of a synchronous system. That is the internal registers or flip flops are synchronized to a common clock.

A synchronous system is made of registers which are in turn made of flip flop. There are various types of flip flop such as SR flip flop, JK flip flops, D flip flop. D flip flop are commonly used in the design of synchronous system. One reason is that D flip flop operates with single input while SR and JK flip flop operates with two inputs.

A D flip flop can be modelled in VHDL in many ways. Here 3 ways of modelling a D flip flop is shown. The VHDL models are simulated using aldec VHDL software.

A D flip flop symbol diagram in proteus professional circuit diagram editor is shown below.

As mentioned earlier latch is level triggered storage device while a flip flop is edge triggered device. The input to the latch is a pulse whose level of logic(usually high) is detected and the the stored bit appears at the output. The flip flop such as D flip flop are driven by the clock input whose edge transition from low to high called positive edge triggered or high to low transition called negative triggered is detected.

Now we will illustrate how to model a D flip flop in VHDL. 3 different ways of modelling a D flip flop will be shown.

First model of D flip flop:

First we will consider positive edge triggered D flip flop.

The first model model1 VHDL code is below. Here sequential process statement without sensitivity list and using wait until statement is used. The wait until statement causes the edge detection.

library ieee;
use ieee.std_logic_1164.all;

entity DFFmodel1 is
    port(
    D, clk : in std_logic;
    Q : out std_logic
    );
end DFFmodel1;

architecture model1 of DFFmodel1 is
begin
    pro : process is
    begin
    wait until (clk = 1);
    Q <= D;
    end process pro;
end model1;

In the above D flip flop model1,the process is not evaluated until clock signal is logic high. Once clock signal goes high(rising edge) the next assignment statement Q<=D is evaluated. This is repeated in the next rising edge of the clock.

The simulation waveform is shown below,

In the above waveform diagram, the input to the flip flop D occurs in the 5th clock cycle but does not appear at the output at this 5th clock cycle. The output at Q appears in the 6th clock cycle on the rising edge of the clock signal.

Second model of D flip flop

This second method uses if then statement within a process with sensitivity list. The if (condition) is the edge detection in this case.

library ieee;
use ieee.std_logic_1164.all;

entity DFFmodel2 is
    port(
    D, clk : in std_logic;
    Q : out std_logic
    );
end DFFmodel2;

architecture model2 of DFFmodel2 is
begin
    pro : process(D,clk)
    begin
    if (clk = 1) then
    Q <= D;
    end if;
    end process pro;
end model2;

In this case notice that there is no wait statement like in the first model.

The simulated waveform in vhdl software aldec is shown below,

This waveform is same as the first one.

Third Model of D flip flop

The 3rd model vhdl code is same as the second but with sensitivity list removed and wait on statement added in the end of the process.

library ieee;
use ieee.std_logic_1164.all;

entity DFFmodel3 is
    port(
    D, clk : in std_logic;
    Q : out std_logic
    );
end DFFmodel3;

architecture model3 of DFFmodel3 is
begin
    pro : process
    begin
    if (clk = 1) then
    Q <= D;
    end if;
    wait on clk;
    end process pro;
end model3;

So this model is like a compromise of the 1st and 2nd model. Here the wait on statement acts like the sensitivity list of a process whose function is to re-evaluate if there is any change of the signal within the sensitivity list.

The waveform will be same as that shown in the above two models(1 and 2).

There is some differences of the 3 models that were illustrated. Before we explain that one must remember that a process can have either sensitivity list or one or more wait statement but not both. VHDL software will error if this happens. As a substitute, one can replace the sensitivity list with wait on statement was was done in the 3rd model.

All of the above model were positive edge triggered D flip flops.

Now at last, we want to show negative edge triggered D flip flop VHDL modelling.

The following code shows this,

library ieee;
use ieee.std_logic_1164.all;

entity negDFFmodel1 is
    port(
    D, clk : in std_logic;
    Q : out std_logic
    );
end negDFFmodel1;

architecture model1 of negDFFmodel1 is
begin
    pro : process is
    begin
    wait until (clk = 0);
    Q <= D;
    end process pro;
end model1;

The following is the simulated waveform. Compare this with the positive edge triggered D flip flop simulated waveform above.

The data D appears at the output Q at the falling edge of the 6th clock pulse.

Similarly we can write the vhdl code for the negative triggered flip flop by replacing the 1 by 0 in the 2nd and 3rd model.

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