How to convert between data types in VHDL

There are basically 4 data types you will encounter in vhdl programming. They are std_logic_vector, unsigned, signed and integers. Normally you would define the interface or ports as std_logic_vector. But while you create hardware that does certain function you need to convert the std_logic_vector to unsigned, signed or integer and back from these to std_logic_vector. The std_logic_vector are simply binary bits which have no information about the mathematical form such as signed or unsigned integer.

Thus we often need to convert the incoming binary bits to unsigned, signed integers. For example if the input bits are numbers on which we want to perform arithmetic operation then we want to convert these input binary bits to unsigned or signed integer and then we can use the mathematical operators.
Mathematical operators like +, -, * and / can be used in the concurrent or sequential statements.

Consider for example that your are designing an arithmetic hardware that takes as inputs two signals a and b of data type std_logic_vector.

If x is a std_logic_vector data type then to convert it to unsigned or signed use-
unsigned(x)
signed(x)

If x is unsigned or signed data type then to convert it to std_logic_vector use-
std_logic_vector(x)

If x is an unsigned or signed then to convert unsigned or signed to integer then use-
to_integer(x)

If x is an integer then you can convert it to unsigned or signed use-
to_unsigned(x,size)
to_signed(x,size)

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